View W39F010_214833.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W39F010 128K x 8 CMOS FLASH MEMORY
1. GENERAL DESCRIPTION
The W39F010 is a 1Mbit, 5-volt only CMOS flash memory organized as 128K x 8 bits. For flexible erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (x 8) data appears on DQ7 - DQ0. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39F010 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
* Single 5-volt operations * Flexible 4K-page size can be used as
- 5-volt Read - 5-volt Erase - 5-volt Program
* Fast Program operation:
Parameter Blocks
* Typical program/erase cycles:
- 1K/10K
* Twenty-year data retention * Low power consumption
- Byte-by-Byte programming: 50 S (max.)
* Fast Erase operation:
- Chip Erase cycle time: 100 mS (max.) - Page Erase cycle time: 25 mS (max.)
* Read access time: 70/90 nS * 32 even pages with 4K bytes * Any individual page can be erased * Hardware protection:
- Active current: 15 mA (typ.) - Standby current: 15 A (typ.)
* End of program detection
- Software method: Toggle bit/Data polling * TTL compatible I/O
* JEDEC standard byte-wide pinouts * Available packages: 32-pin 600 mil DIP,
- Optional 16K byte Top/Bottom Boot Block with lockout protection
32-pin PLCC, 32- pin STSOP (8 x 14 mm) and 32- pin TSOP
-1-
Publication Release Date: June 17, 2002 Revision A2
W39F010
3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM
DQ 0 - DQ 7
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27
VDD
VDD #WE NC A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3
Vss
Erase Voltage Generator
Input / output Buffers
#WE
32-pin DIP
26 25 24 23 22 21 20 19 18 17
State Control Command Register Program Voltage Generator
#CE #OE
VDD Detect Timer A d d r e s s L a t c h
Chip Enable Output Enable Logic
Data latch
Y-Decode
Y-MUX / SENSING
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
A 1 5 3
A 1 6 2
N C
V# DW DE
N C
X-decode ARRAY
1 32 31 30 29 28 27 A14 A13 A8 A9 A11 #OE A10 #CE DQ7
A 0 - A 16
32-pin PLCC
26 25 24 23 22 21
14 15 16 17 18 19 20
5. PIN DESCRIPTION
SYMBOL
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
D Q 1
DV QS 2S
D Q 3
D Q 4
D Q 5
D Q 6
PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connections
A11 A9 A8 A13 A14 NC #WE VDD NC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-pin TSOP
#OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
A0 - A16 DQ0 - DQ7 #CE #OE #WE VDD VSS NC
-2-
W39F010
6. FUNCTIONAL DESCRIPTION
Device Bus Operation
Read Mode
The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details.
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state, while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Standby Mode
There are two ways to implement the standby mode on the W39F010 device, both using the #CE pin.
A CMOS standby mode is achieved with the #CE input held at VDD 0.5V. Under this condition the current is typically reduced to less than 50 A. A TTL standby mode is achieved with the #CE pin held at VIH.
Under this condition the current is typically reduced to 2 mA. In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
Data Protection
The W39F010 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
-3-
Publication Release Date: June 17, 2002 Revision A2
W39F010
Boot Block Operation
There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes or first 16K bytes of the memory with the address range from 1C000(hex) to 1FFFF(hex) for top location or 00000(hex) to 03FFF(hex) for bottom location. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. In order to detect whether the boot block feature is set on the first/last 16K-byte block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first(bottom) location or 1FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data is "1," the 16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data is "0," the lockout feature will be inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W39F010 locks out when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when VDD is less than 2.0V typical. The W39F010 ignores all write and read operations until VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences.
-4-
W39F010
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 = A1). To terminate the operation, it is necessary to write the auto-select exit command sequence into the register.
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s. Refer to the Programming Command Flow Chart using typical command strings and bus operations. Publication Release Date: June 17, 2002 Revision A2
-5-
W39F010
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each pages at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Erase Command Flow Chart using typical command strings and bus operations.
Page Erase Command
Page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the page erase command. The page address (any address location within the desired page) is latched on the falling edge of #WE, while the command (50H) is latched on the rising edge of #WE. Page erase does not require the user to program the device prior to erase. When erasing a page, the remaining unselected pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations.
Write Operation Status
DQ7: Data Polling
The W39F010 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase #WE pulse. Data Polling must be performed at addresses within any of the pages being erased. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on -6-
W39F010
DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0- DQ6 may be still invalid. The valid data on DQ0 - DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or page erase time-out (see "Command Definitions").
DQ6: Toggle Bit
The W39F010 also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For page erase, the Toggle Bit is valid after the last rising edge of the page erase #WE pulse. The Toggle Bit is active during the page erase time-out. Either #CE or #OE toggling will cause DQ6 to toggle.
7. TABLE OF OPERATING MODES
Device Bus Operations
MODE #CE Read Write Standby Write Inhibit Output Disable VIL VIL VIH
X X
PIN #OE VIL VIH X
VIL X
#WE VIH VIL X
X VIH
DQ0 - DQ7 Dout Din High Z
High Z/Dout High Z/Dout
VIL
VIH
VIH
High Z
-7-
Publication Release Date: June 17, 2002 Revision A2
W39F010
Command Definitions
COMMAND DESCRIPTION Read Chip Erase Page Erase Byte Program Top Boot Block Lockout -16KByte Bottom Boot Block Lockout - 16KByte Product ID Entry Product ID Exit Product ID Exit
(2) (2)
NO. OF Cycles 1 6 6 4 6 6 3 3 1
1ST CYCLE Addr. (1)Data AIN 5555 5555 5555 5555 5555 5555 5555 XXXX DOUT AA AA AA AA AA AA AA F0
2ND CYCLE Addr. Data
3RD CYCLE Addr. Data
4TH CYCLE Addr. Data
5TH CYCLE Addr. Data
6TH CYCLE Addr. Data
7TH CYCLE Addr. Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55 55 55
5555 5555 5555 5555 5555 5555 5555
80 80 A0 80 80 90 F0
5555 5555 AIN 5555 5555
AA AA DIN AA AA
2AAA 2AAA
55 55
5555 PA(3)
10 50
2AAA 2AAA
55 55
5555 5555
70 70
1FFFF 00000
XX(4) XX(4)
Notes: 1. Address Format: A14 - A0 (Hex); Data Format: DQ7 - DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. PA: Page Address PA = 1FXXXh for Page 31 PA = 1EXXXh for Page 30 PA = 1DXXXh for Page 29 PA = 1CXXXh for Page 28 PA = 1BXXXh for Page 27 PA = 1AXXXh for Page 26 PA = 19XXXh for Page 25 PA = 18XXXh for Page 24 PA = 17XXXh for Page 23 PA = 16XXXh for Page 22 PA = 15XXXh for Page 21 PA = 14XXXh for Page 20 PA = 13XXXh for Page 19 PA = 12XXXh for Page 18 PA = 11XXXh for Page 17 PA = 10XXXh for Page 16 4. XX: Don't care PA = 0FXXXh for Page 15 PA = 0EXXXh for Page 14 PA = 0DXXXh for Page 13 PA = 0CXXXh for Page 12 PA = 0BXXXh for Page 11 PA = 0AXXXh for Page 10 PA = 09XXXh for Page 9 PA = 08XXXh for Page 8 PA = 07XXXh for Page 7 PA = 06XXXh for Page 6 PA = 05XXXh for Page 5 PA = 04XXXh for Page 4 PA = 03XXXh for Page 3 PA = 02XXXh for Page 2 PA = 01XXXh for Page 1 PA = 00XXXh for Page 0
-8-
W39F010
Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause T BP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
-9-
Publication Release Date: June 17, 2002 Revision A2
W39F010
Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle Bit Successfully Completed
Pause T EC /TPEC
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Individual Page Erase Command Sequence (Address/Command): 5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Page Address/50H
- 10 -
W39F010
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the page addresses within the page being erased during page erase operation =Any of the device addresses being erased during chip operation
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes
DQ6 = Toggle ? No Pass
- 11 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
Boot Block Lockout Enable Flow Chart
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Pause T BP
Load data 80 to address 5555
Exit
Load data AA to address 5555
Load data 55 to address 2AAA Load data 70 to address 5555 Load data XX to address 1FFFF/0
70 to lock 16K Boot Block
1FFFF(XX) to lock Top Boot Block 00000(XX) to lock Bottom Boot Block
- 12 -
W39F010
Software Product Identification and Boot Block Lockout Detection Flow Chart
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 0000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 0001 data = A1
(2)
Load data F0 to address 5555
Pause 10 S
Read address=02/1FFF2 for Bottom/Top data: in DQ1="1" or "0" for 16K Boot Block
(4)
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 or DQ1= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 or DQ1= " 0 ," the lockout feature is inactivated and the matched boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
- 13 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
8. DC CHARACTERISTICS
Absolute maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature Voltage on Any Pin to Ground Potential Except A9 Voltage on A9 Pin to Ground Potential RATING -2.0 to +7.0 0 to +70 -65 to +125 -2.0 to +7.0 -2.0 to +13.0 UNIT V C C V V
Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD = 5V 0.5V, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz Other inputs = VIL/VIH
LIMITS MIN. TYP. MAX. 30
UNIT mA
Power Supply Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
IDD
-
15
ISB1 #CE = VIH, all DQs open #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ VSS VIN = VSS to VDD VOUT = VSS to VDD IOL = 2.1 mA
-0.3 2.0 2.4
1 15 -
2 50 1 1 0.8 VDD +0.5 0.45 -
mA A A A V V V V
ISB2 ILI ILO VIL VIH VOL
VOH IOH = -0.4 mA
Pin Capacitance
(VDD = 5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
CONDITIONS VIN = 0V VOUT = 0V
TYP. 6 10
MAX. 8 12
UNIT pF pF
- 14 -
W39F010
9. AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V <5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+5V
1.8K
DOUT
30 pF (Including Jig and Scope)
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
- 15 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5V 0.5V, VSS = 0V, TA = 0 to 70 C)
PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE Low to Active Output #OE Low to Active Output #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change
SYMBOL TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH
W39F010-70 MIN. 70 0 0 0 MAX. 70 70 35 25 25 -
W39F010-90 MIN. 90 0 0 0 MAX. 90 90 45 25 25 -
UNIT nS nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte programming Time Chip Erase Cycle Time Page Erase Cycle Time SYMBOL TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBP TEC TEP MIN. 0 40 0 0 0 0 100 100 100 40 10 TYP. 35 50 12.5 MAX. 50 100 25 UNIT nS nS nS nS nS nS nS nS nS nS nS S mS mS
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 16 -
W39F010
AC Characteristics, continued
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
Data Polling and Toggle Bit Timing Parameters
PARAMETER #OE to Data Polling Output Delay #CE to Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay SYM. TOEP TCEP TOET TCET W39F010-70 MIN.
-
W39F010-90 MIN.
-
UNIT
nS nS nS nS
MAX.
35 70 35 70
MAX.
45 90 45 90
- 17 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
10. TIMING WAVEFORMS
Read Cycle Timing Diagram
T RC Address A16-0 TCE #CE
#OE
TOE
VIH #WE
TOLZ
TOHZ
TCLZ High-Z DQ7-0
T OH Data Valid TAA
TCHZ High-Z Data Valid
#WE Controlled Command Write Cycle Timing Diagram
TAS Address A16-0
TAH
#CE
TCS TOES
TCH TOEH
#OE TWP TWPH
#WE
TDS DQ7-0 Data Valid
TDH
- 18 -
W39F010
Timing Waveforms, continued
#CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A16-0 TCPH TCP #CE TOES #OE TOEH
#WE TDS DQ7-0 High Z Data Valid
TDH
Chip Erase Timing Diagram
Six-byte code for 5V-only software chip erase Address A16-0 5555 2AAA 5555 5555 2AAA 5555
DQ7-0 #CE
AA
55
80
AA
55
10
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEC
Internal Erase starts
- 19 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
Timing Waveforms, continued
Page Erase Timing Diagram
Six-byte commands for 5V-only Page Erase Address A16-0 5555 2AAA 5555 5555 2AAA PA
DQ7-0 #CE
AA
55
80
AA
55
50
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEP
Internal Erase starts
PA = Page Address Please refer to page 9 for detail information
#DATA Polling Timing Diagram
Address A16-0 #WE
An
An
An
An
TCEP #CE TOEH #OE TOEP DQ7 X X TBP or TEC X X TOES
- 20 -
W39F010
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A16-0
#WE
#CE TOEH #OE TOES
DQ6 TBP orTEC
- 21 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
11. ORDERING INFORMATION
PART NO. W39F010-70 W39F010-90 W39F010T-70 W39F010T-90 W39F010Q-70 W39F010Q-90 W39F010P-70 W39F010P-90 W39F010-70B W39F010-90B W39F010T-70B W39F010T-90B W39F010Q-70B W39F010Q-90B W39F010P-70B W39F010P-90B
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
ACCESS POWER SUPPLY STANDBY VDD TIME CURRENT MAX. CURRENT MAX. (nS) 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 (mA) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 (mA) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 32-pin DIP 32-pin DIP
PACKAGE
CYCLE 1K 1K 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 10K 10K
32-pin TSOP (8 mm x 20 mm) 32-pin TSOP (8 mm x 20 mm) 32-pin STSOP (8 mm x 14 mm) 32-pin STSOP (8 mm x 14 mm) 32-pin PLCC 32-pin PLCC 32-pin DIP 32-pin DIP 32-pin TSOP (8 mm x 20 mm) 32-pin TSOP (8 mm x 20 mm) 32-pin STSOP (8 mm x 14 mm) 32-pin STSOP (8 mm x 14 mm) 32-pin PLCC 32-pin PLCC
- 22 -
W39F010
12. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin PLCC W39F010P-70
W39F010P-70 2138977A-A12 149OBSA
1 line: winbond logo 2 line: the part number: W39F010P-70 3 line: the lot number 4 line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code
th rd nd st
- 23 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
13. PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
16
eA S Notes:
E c
S
A A2 L B B1
A1
Base Plane Seating Plane
e1
a
eA
1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec.
32-pin TSOP (8 x 20 mm)
HD
Symbol
Dimension in Inches Min. Nom. Max.
0.047 0.006 0.041 0.009 0.007 0.728 0.319 0.795
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A2
__
0.002 0.037 0.007 0.005 0.720 0.311 0.780
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031
__
0.05 0.95 0.17 0.12 18.30 7.90 19.80
__ __
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
M
e E
b c D
0.10(0.004)
b
E HD e L L
A A2 L L1 A1
1
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y
__
3
__
3
Y
Note:
Controlling dimension: Millimeters
- 24 -
W39F010
Package Dimensions, continued
32-pin PLCC
HE E
4
1
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
GD D HD
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
L A2 A
Seating Plane
e
b b1 GE
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc.
32-pin STSOP (8 x 14 mm)
HD D c
Dimension in Inches Dimension in mm Symbol Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.024 0.031 0.000 0 3 0.004 5 0.00 0 3 0.028 0.50 0.006 0.041 0.010 0.008 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.60 0.80 0.10 5 0.70
Min. Nom. Max.
1.20 0.15 1.05 0.27 0.21
e
E
b
c
L L1
A1 A2 A
Y
A A1 A2 b c D E HD e L L1 Y
- 25 -
Publication Release Date: June 17, 2002 Revision A2
W39F010
14. VERSION HISTORY
VERSION A1 A2 DATE Dec. 2000 June 17, 2002 PAGE 1, 23 1 4 10, 11, 12 10 11 16 1, 23 24 Initial Issued Add cycle of 1K Change active current from 10 to15mA (typ.) Change standby current from 20 to15 A (typ.) Modify Low VDD Inhibit Delete old flow chart and add Embedded Algorithm Remove Block Erase from the Embedded Erase Algorithm Correct Embedded #Data Polling Algorithm Change IDD from 10/20 mA to15/30 mA (typ./max.) Change ISB2 from 20/50 A to15/50 A (typ./max.) Rename TSOP (8 x 14 mm) as STSOP (8 x 14 mm) Add HOW TO READ THE TOP MARKING DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 26 -

▲Up To Search▲

Price & Availability of W39F010

	To Download W39F010 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .